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2022 年 12 月 16 日，达坦科技联结 SpinalHDL 社区，举办了 SpinalHDL Webinar 2022。在题为《SpinalHDL 利用前景摸索》的线上研讨会上，九位分享人在三个探讨分主题下做了各自畛域内利用 Spinal HDL 的实际、挑战和教训的分享。
分主题一：数据通路减速（Datapath/Accelerations）
1、分享人：Tianrui Li
演讲主题: Utilizing SpinalHDL for large-scale datapath design
演讲摘要: This presentation introduces the experience and case of large-scale data path design using SpinalHDL with functional programming and third-party libraries. Take a completely parallel elliptic curve adder as an example.
2、分享人：Jeff-Ciesielski
演讲主题：Utilizing SpinalHDL to Accelerate Neuroscience
演讲摘要：This presentation covers how LeafLabs leverages SpinalHDL to enable the rapid development of a devices used for Neuroscience research ranging from mixed-signal Electrophysiology ASICs to FPGA based designs for system control and USB3 connectivity.
3、分享人：Teilraum
演讲主题：A Network Attached Deep Learning Accelerator for FPGA Clusters
演讲摘要：This presentation introduces a Layer parallel framework for DNN training on an FPGA cluster. All hardware description is done using SpinalHDL. It gives an overview of approaches and examples where SpinalHDL came in handy.
分主题二：简单零碎设计案例（Design）
1、分享人：Saahm
演讲主题：SpinalHDL in Computer Architecture Research. A) MicroRV32 Platform and B) FPGA-based Heterogeneous Real-Time Systems with RISC-V
演讲摘要：The presentation covers two topics in which SpinalHDL aided in the Research of Computer Architecture. MicroRV32 is a RISC-V SoC Platform built with SpinalHDL for research and education aligned along a RISC-V Virtual Prototype in SystemC TLM. The second topic covers a topic on Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems. There the VexRiscv-based Murax SoC was used on an FPGA as a Heterogeneous Real-time System for a Case-Study.
2、分享人：Distributed
演讲主题：Title: Coding a microprogrammed protocol receiver in SpinalHDL
演讲摘要：This presentation introduces a microcode-like approach to coding a communications protocol receiver used in flying, handheld and stationary 3D scanners. Decoding the protocol in random logic leads to unattractively high resource usage. Therefore, a microprogrammed approach was chosen where data out of preprogrammed memories controls the rather regularly organized data path. The talk highlights the construction of the microinstructions and their physical representation, showing how code evaluated at Scala runtime can be elegantly intertwined with Spinal code representing hardware.
3、分享人：Dolu1990
演讲主题：NaxRiscv : A Pipeline / Plugins / SpinalHDL / Scala mix
演讲摘要：This presentation / live demo shows how the NaxRiscv project (Out-of-order / superscalar RISC-V CPU) mix Scala and the SpinalHDL API to describe its hardware. By many aspect, it goes beyond the VexRiscv project, and should provide some usefull / interresting design patterns for the public.
分主题三：硬件设计流程（Flow）
1、分享人：Readon
演讲主题：Recent progress on formal verification support on SpinalHDL
演讲摘要：The formal verification is a technology to verify design, which helps to find the corner cases. SpinalHDL have provided an integration of this tech with SymbiYosys easily. The brief introduction on how to verify a design would be presented by example. Some new build blocks helping to simplify the verification process would be introduced. At last, a short overview of the verification of some facilities in SpinalHDL’s lib would also be summarized.
2、分享人：Sebastien-riou
演讲主题：SpinalHDL for ASIC
演讲摘要：The presentation is a highlights of a ASIC done entirely in SpinalHDL, fabricated in GF22FDX. Focus on pads, RAMs and FPGA for ASIC verification.
3、分享人：Andreas Wallner
演讲主题：From Peripheral Plugins to Product documentation.
演讲摘要：The presentation shows how we can go from a simple plugin system for bus peripherals using register file generators to documentation using custom Sphinx plugins. Also shows some insight into ongoing development of a lab communication device for in-the-loop testing.
欲观看此次 SpinalHDL 利用前景摸索线上研讨会，请点击链接：SpinalHDL 利用前景摸索线上研讨会。
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