关于systemverilog:UVMC学习笔记四在SystemCC-layer的信息汇报控制
前言在uvmc中能够提供对uvm testbench根本档次信息的打印和信息打印级别的管制,管制过程能够systemC layer实现操作 一. UVM testbench topology 例化档次信息打印uvmc_print_topology(context,depth)参数阐明: context: 开始打印拓扑的组件的层次结构门路。如果未指定,则拓扑打印将从uvm_top开始。能够应用通配符(*和)指定多个组件,例如“top.env.* .driver”。可通过将contxt括在前斜杠中来指定POSIX扩大正则表达式,例如“/a[hp]b/”。默认值:" (uvm_top)、 depth:要打印的层次结构的级别数。如果没有指定,则打印从给定上下文开始的所有层次结构。默认值:-1(递归所有子元素) 例子: void top::show_uvm_print_topology(){ cout << endl << endl << "Waiting for UVM to reach build phase..." << endl; uvmc_wait_for_phase("build", UVM_PHASE_STARTED); cout << endl << endl << "Topology before build phase:" << endl; uvmc_print_topology(); uvmc_wait_for_phase("build", UVM_PHASE_ENDED); cout << endl << endl << "Topology after build phase:" << endl; uvmc_print_topology();}打印后果: Topology before build phase:UVM_INFO /home/shawntan/Project/uvmc/uvmc-2.3.2/src/connect/sv/uvmc_commands.sv(502) @ 0 ns: reporter [TRACE/UVMC_CMD/PRINT_TOPOLOGY] Topology for component uvm_top:----------------------------------------------------------------------Name Type Size Value----------------------------------------------------------------------<unnamed> uvm_root - @172 prod_out UVMC_PROXY_FOR_uvm_tlm_b_transport_port - @366 sb_actual_in UVMC_PROXY_FOR_uvm_analysis_export - @382 e env - @336 prod_out uvm_tlm_b_transport_port - @345 sb_actual_in uvm_analysis_export - @355 ---------------------------------------------------------------------- UVM_INFO /home/shawntan/Project/uvmc/uvmc-2.3.2/src/connect/sv/uvmc_commands.sv(208) @ 0 ns: reporter [UVMC_WAIT_FOR_PHASE] Waiting for phase 'build' to be 'UVM_EQ' to state 'UVM_PHASE_ENDED'. Currently its state is 'UVM_PHASE_EXECUTING'Topology after build phase:UVM_INFO /home/shawntan/Project/uvmc/uvmc-2.3.2/src/connect/sv/uvmc_commands.sv(502) @ 0 ns: reporter [TRACE/UVMC_CMD/PRINT_TOPOLOGY] Topology for component uvm_top:-----------------------------------------------------------------------------Name Type Size Value-----------------------------------------------------------------------------<unnamed> uvm_root - @172 prod_out UVMC_PROXY_FOR_uvm_tlm_b_transport_port - @366 sb_actual_in UVMC_PROXY_FOR_uvm_analysis_export - @382 e env - @336 prod producer - @402 analysis_out uvm_analysis_port - @422 out uvm_tlm_b_transport_port - @412 prod_out uvm_tlm_b_transport_port - @345 sb scoreboard - @432 actual_in uvm_analysis_imp - @441 exp_fifo uvm_tlm_analysis_fifo #(T) - @461 analysis_export uvm_analysis_imp - @510 get_ap uvm_analysis_port - @500 get_peek_export uvm_get_peek_imp - @480 put_ap uvm_analysis_port - @490 put_export uvm_put_imp - @470 expect_in uvm_analysis_export - @451 sb_actual_in uvm_analysis_export - @355 -----------------------------------------------------------------------------能够看到通过phase管制当前,build phase 前后所print 的testbench topology的构建档次后果存在显著的差别 ...